A prior art non-inverting TTL buffer circuit useful for example as an output buffer line driver is illustrated in FIG. 1. Data signals at high and low potential levels at the input V.sub.IN propagate through the buffer circuit and are transmitted as output data signals at the output V.sub.OUT in phase with the input data signals. A pullup circuit provided by Darlington transistor pair Q5, Q6 sources current to the output V.sub.OUT from high potential power rail V.sub.CC through resistor R5 and diode D8. The pulldown transistor element Q4 sinks current from the output V.sub.OUT to the low potential power rail GND. Resistor R6 and Diode D6 provide a leakage path for discharge of the base of pulldown transistor element Q4 when it is not to be conducting. The phase splitter transistor element Q3 controls in opposite phase the conducting states of the pullup and pulldown transistor elements.
The phase splitter transistor element Q3 is an inverting stage. The coupling of the pullup circuit Q5, Q6 to the collector node of the phase splitter Q3 results in an inverted signal at the output V.sub.OUT. Therefore to provide a non-inverting buffer circuit, a second invertor stage transistor element QB is added to the buffer circuit. The base node of phase splitter Q3 is coupled to the collector node of the invertor stage transistor element QB to provide the second inverting coupling. Base drive current to phase splitter Q3 through resistor RB is controlled by the conducting state of inverting stage transistor element QB. Diode DB provides the emitter current path to low potential power rail GND for transistor element QB. Leakage resistor RG discharges the base of transistor element QB when it is not conducting.
The input circuit of the buffer circuit of FIG. 1 includes the input diode D1 and input transistor element QA. A low potential signal at the input V.sub.IN diverts base drive current through resistor R1 away from the base node of input transistor QA turning it off. A high potential signal at the input V.sub.IN directs base drive current to turn on the input transistor element QA which in turn conducts base drive current to the invertor stage transistor element QB through resistor RA. Transistor elements QA and QB are therefore conducting in phase with the input data signal. The collector nodes of transistor elements QB and Q3 provide the sequential inverting couplings so that the data signal at the output V.sub.OUT is in phase with the input V.sub.IN.
Another prior art non-inverting buffer circuit is illustrated in FIG. 2 with an added stage of gain. The additional stage of amplification is provided by voltage amplifier stage transistor element QA1 which provides amplified base drive current to the base node of invertor stage transistor element QB through resistor RA1. In the example of FIG. 2, transistors QA, QA1 and QB operate in phase with the input signal at the input V.sub.IN. Base drive current to the phase splitter transistor element Q3 through resistor RB1 is controlled by the inverting coupling at the collector node of invertor stage transistor element QB through diode DB1. The remaining components performing the functions similar to that in FIG. 1 are indicated by the same reference designations. The circuit of FIG. 2 may be used where additional gain is necessary for example where transistor elements with low .beta.'s are used.
A disadvantage of the prior art non-inverting buffer circuits of FIGS. 1 and 2 is of course the requirement that additional stages be added for inversion or gain substantially increasing signal propagation delay through the circuits. The additional stages also require increased power consumption. Other operating features of the prior art non-inverting buffer circuits of FIGS. 1 and 2 which it would be desirable to improve include temperature dependence, ground noise, including ground bounce and undershoot, noise margin at the input, switching speed etc.